Lab 2: FPGA Logic Design

Orientation

From logic gates to configured hardware

Equipment

Learn the DE0-Nano board

Before you build anything, use the DE0-Nano board guide to find the basic board information below. You do not need to memorize it. Open the guide, find each answer, and type it into the matching box.

Safety first.
Keep the board on a non-conductive surface. Turn power off before moving wires. Only program the board after the USB-Blaster and board connection are secure.

Need help finding these answers?
→ DE0-Nano Board Reference

Setup

Create a Quartus Prime project

1. Open Quartus Prime 25.1 Lite Edition.
2. Choose File → New Project Wizard. Create a writable project folder; use a short project name and use the same top-level entity name for the first design.
3. Select Empty project; do not add files yet.
4. Select the Cyclone IV E target device EP4CE22F17C6. Review the project summary and finish.
5. Save the project before creating a design file.

Need a refresher?
→ Creating a Quartus Prime Project · → Selecting the Target FPGA

Schematic design

Build the first AND gate

1. Create a Block Diagram/Schematic File and save it using the project top-level name.
2. Open the Symbol dialog. Under Primitives → Logic, place an and2 primitive.
3. Under Primitives → Pin, add two input pins and one output pin. Name them A, B, and F.
4. Wire A and B to the AND inputs and wire F to the output. Save.
5. Start Compilation. Correct errors, save, and compile again until successful.

Need a refresher?
→ Block Diagram/Schematic Files · → Compiling a Design

Hardware verification

Assign pins, program, and verify

1. Open Assignments → Pin Planner. Assign the input and output ports to the required DE0-Nano switch and LED pins. Confirm each assignment against the board reference.
2. Save, then compile again so the assignment changes are included.
3. Open Tools → Programmer. Select USB-Blaster, use JTAG mode, and add the compiled .sof from output_files.
4. Start programming. The .sof is the compiled SRAM configuration file loaded into the FPGA for the current design.
5. Test all A/B combinations using the assigned DIP switches and LED output. Show the working AND gate to the instructor.

Logic gates

Implement and verify logic gates

Create and test OR, NAND, NOR, XOR, and XNOR using the same project flow. Replace the primitive, save, compile, assign pins if needed, program the FPGA, and test every DIP-switch combination. Enter the predicted output and your LED observation.

Need a refresher?
→ Basic Logic Gates · → Truth Tables

Combinational design

Implement the supplied combinational circuit

Using the supplied circuit diagram, analyse the function, build the complete schematic, compile it, assign the required I/O, program the FPGA, and verify the output combinations on the board. Do not simplify the circuit until you have recorded its required behaviour.

Verilog HDL

Describe combinational hardware with Verilog

A schematic describes hardware graphically. Synthesizable Verilog describes the intended hardware with modules, ports, and logic expressions; synthesis converts that description into FPGA logic.

1. Create File → New → Verilog HDL File, then save it with the file name of your choice.
2. Define one module whose name matches with your file name. Declare its inputs and outputs, then implement the specified combinational behaviour.
3. Add the saved file to the project and confirm it appears in project files. Save all.
4. Run Analysis & Synthesis, correct syntax errors, and confirm the top-level entity is correct.

Need a refresher?
→ Verilog Modules and Ports · → Combinational Logic in Verilog

module light (LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7);
	output LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7; //LEDs 

	reg [7:0] LEDs = 8'b10110000;

	assign LED0 = LEDs[0]; 
	assign LED1 = LEDs[1];
	assign LED2 = LEDs[2];
	assign LED3 = LEDs[3];
	assign LED4 = LEDs[4];
	assign LED5 = LEDs[5];
	assign LED6 = LEDs[6];
	assign LED7 = LEDs[7];
endmodule

Type or paste this starter code into your Verilog HDL file. The file name and top-level module must match your file name.

Build and test

Compile the design and test the board

Now turn your Verilog file into a working FPGA program. Follow these steps in order.

1. In Quartus, run Analysis & Synthesis. Then choose Tools → Netlist Viewers → RTL Viewer.
2. Take a screenshot of the RTL Viewer. This shows the logic Quartus found in your Verilog file.
3. Open Pin Planner. Enter the LED and switch pin numbers, save, and compile the project again.
4. Open Programmer, select USB-Blaster, load the new .sof file, and click Start. Test the LEDs and switches on the board.

Analysis

Think it through

Completion

Review and create the local submission ZIP

Demonstrate the completed laboratory work and your programming checklist to the instructor. The ZIP retains the required responses and files selected in this browser session.